1. Field of the Invention
The present invention pertains to a drive circuit for semiconductor power switching elements.
2. Description of the Related Art
Inverter devices are well known wherein a first switching element and a second switching element are respectively placed on a low voltage side arm (below called the “lower side”) and a high voltage side arm (below called the “upper side”), the two arms being connected between the terminals of a main power supply, and the first and the second switching elements are connected in series.
In such a device, the second switching element connected to the upper side is driven in a floating potential state with respect to the reference potential, and the drive circuit includes a power supply externally insulated from a transformer. Also, in order to transmit drive signals from the low voltage side circuit to the high voltage side circuit, a level shifting (below called lower to upper level shift) device is necessary for which the transmission of a signal is possible even in the floating potential state.
Moreover, the level shifters performing signal transmission from the high voltage side circuit to the low voltage side circuit are called upper to lower level shifters. The integrated circuit (IC) incorporating these is usually called a gate driver IC. A lower to upper level shift circuit such as this is e.g. described in JP-A-9-172366.
FIG. 7 is a circuit diagram showing the configuration of the drive circuit of the prior art semiconductor device shown in FIG. 2 of JP-A-9-172366. In FIG. 7, an IGBT (Insulated Gate Bipolar Transistor) 24, being the switching element of an upper arm 232, and an IGBT 25, being the switching element of a lower arm 233, are connected in series to both terminals of a main power supply 23 and constitute a half bridge. The cathode side of main power supply 23 is at earth (ground) potential Ve.
Freewheel diodes 26 and 27 are connected to IGBT 24 and IGBT 25. And then, a load 28 (an inductive load like a motor) is connected to connection point 251 of IGBT 24 and IGBT 25.
IGBT 24 of upper side 232 operates as a switch, with contact point 251 of upper side 232 and lower side 233 as the reference voltage. An upper-side regulating power supply 21 supplying power to a drive circuit and protection circuit 39 for the upper side is externally insulated by means of a transformer not illustrated.
IGBT 25 of lower side 233 operates as a switch with the ground potential as the reference voltage. A lower-side regulating power supply 22 supplying power to a drive circuit and protection circuit 40 for the lower side is externally insulated by means of a transformer.
Next, an explanation of the circuit driving IGBT 24 of upper side 232 will be given. A pulse generating circuit 31 generates, in response to an input signal supplied by an externally provided microcomputer (not illustrated) or the like, pulse shape on/off signals. Two output terminals thereof are respectively connected to the gate electrodes of level shifting high voltage nMOSFET (n-type Metal Oxide Semiconductor Field Effect Transistor) 32 and high voltage nMOSFET 33.
The drain electrodes of high breakdown voltage nMOSFET 32 and high breakdown voltage nMOSFET 33 are respectively connected to one terminal portion of resistances 35, 34 as well as to the input sides of inverter circuits 41, 45. Zener diodes 36, 37 are connected in parallel to resistances 34, 35.
The outputs of inverter circuits 41, 45 are in addition connected to a set input (S) and a reset(R) input of a flip-flop circuit 38 via inverter circuits 42, 46, and through filters composed of resistances 43, 47 and capacitors 44, 48. The output (Q)of flip-flop circuit 38 is connected to drive circuit and protection circuit 39. IGBT 24 of upper side 232 is driven by drive circuit and protection circuit 39.
With the drive circuit for the upper side 232 such as this, IGBT 24 of upper arm 232 changes abruptly, by the switching operation of IGBT 25 of lower arm 233, from 0 V up to the rated voltage of main power supply 23 or more, with point 251 of contact with IGBT 25 of lower arm 233 as the reference potential (reference potential of regulating power supply 21 of upper arm 232).
Since there exists a parasitic capacitance C between the drain and source of nMOSFET 32 and nMOSFET 33, when a particularly fast dV/dt transient is generated, the current obtained by multiplying parasitic capacitance C and the dV/dt transient (hereafter called “dV/dt current”) flows simultaneously through high voltage nMOSFET 32 and high breakdown voltage nMOSFET 33.
The dV/dt current flowing in high breakdown voltage nMOSFET 32 and high voltage nMOSFET 33 is at the same level as the current normally flowing during switching, and there arises a voltage drop across resistances 34, 35 at the same time. Because of this, it simultaneously comes about that a set signal and a reset signal are supplied to the set input and the reset input of flip-flop circuit 38.
In general, simultaneously inputting a set signal and a reset release signal to the set input and the reset input of flip-flop circuit 38 is forbidden and leads to unpredictable operation.
The fact that, in order to prevent unpredictable operation such as this, one should set the resistance value of resistances 34, 35 and the first threshold value of inverters 41, 42 to distinguish the voltage drop across resistances 34, 35 due to the dV/dt transient and the voltage drop due to the signal from pulse generation circuit 31, makes a setting with extremely high precision necessary. In JP-A-9-172366, for the case of high dV/dt transients, it is suggested to carry out a measure against erroneous dV/dt operation by means of pulse filters configured with resistances 43, 47 and capacitors 44, 48.